A Phase Locked Loop (PLL) is an electrical circuit usable to generate a synthesized oscillating signal according to a reference signal. In some applications, such as in a radio frequency synthesizer circuit, the frequency of the synthesized oscillating signal is so high that direct comparison of the synthesized oscillating signal and the reference signal is technically and/or economically infeasible. Under these circumstances, a PLL usually uses a frequency divider to generate a pre-scaled feedback signal based on the synthesized oscillating signal divided by a predetermined ratio N or (N+f), where N is a positive integer, and f is a fraction. The synthesized oscillating signal is then considered to be “locked” with the reference signal when the frequency and/or phase of the pre-scaled feedback signal and that of the reference signal are substantially the same. In many applications, a significant portion of overall power consumption of the PLL is attributable to the operation of the frequency divider.